In recent years, with a trend toward a higher density and a higher degree of integration for a semiconductor integrated circuit (hereinafter, abbreviated as a “semiconductor”) chip used for electronic equipment, the number of pins of electrode terminals of a semiconductor chip has been increased and the pitch thereof has been decreased rapidly. For mounting these semiconductor chips on circuit boards, flip chip mounting is used widely in order to decrease a wiring delay.
In this flip chip mounting, solder bumps generally are formed on electrode terminals of the semiconductor chip, which then are joined to connection terminals formed on the circuit board with these solder bumps at one time.
However, in order to mount a next-generation semiconductor chip having more than 5,000 electrode terminals on a circuit board, it is necessary to form solder bumps that correspond to a narrow pitch of 100 μm or less, but it is difficult to adapt to it with a current technique for forming solder bumps.
Moreover, since it is necessary to form a large number of solder bumps that correspond to the number of the electrode terminals, the productivity has to be raised by shortening a mounting cycle for each chip, in order to achieve a cost reduction.
Similarly, in the semiconductor chip, the increase in the number of the electrode terminals has brought about a transition from peripheral-disposed electrode terminals to area-disposed electrode terminals.
Moreover, due to the demands for a higher density and a higher degree of integration, a semiconductor process is expected to develop from 90 nm to 65 nm and further to 45 nm. As a result, the wiring becomes even finer, and the formation of the solder bumps on the area-disposed electrode terminals and the flip chip mounting of the semiconductor chip become difficult.
Thus, there is a demand for a flip chip mounting method that is adaptable to a decrease in thickness and an increase in density due to the future development of the semiconductor process.
Conventionally, as a technique for forming solder bumps, plating, screen printing and the like have been developed. The plating is suitable for a narrow pitch, but has a problem in productivity due to its complicated processes. On the other hand, the screen printing has excellent productivity, but is not suitable for narrowing a pitch because of the use of a mask.
In the light of the problems described above, several techniques for forming solder bumps selectively on electrode terminals of a semiconductor chip or a circuit board have been developed recently. These techniques not only are suitable for forming fine solder bumps but also have excellent productivity because they can form the solder bumps all at one time, and attract attention as techniques that are adaptable to the mounting of the next-generation semiconductor chip on the circuit board.
One of these techniques is called a solder paste method. In this technique, a solder paste, which is a mixture of solder particles and flux, is applied solidly onto a circuit board whose surface is provided with electrode terminals, and the circuit board is heated so as to melt the solder particles, whereby solder bumps are formed selectively on the electrode terminals that have a high wettability (see Patent document 1, for example).
Moreover, in a technique called a super solder method, a paste-like composition (chemical reaction deposition-type solder) that contains an organic acid lead salt and metal tin as main components is applied solidly onto a circuit board on which electrode terminals are formed, and the circuit board is heated so as to cause a substitution reaction between Pb and Sn, thereby depositing a Pb/Sn alloy selectively on the electrode terminals of the board (see Patent document 2, for example).
A conventional flip chip mounting further requires a process of injecting a resin called an underfill between the semiconductor chip and the circuit board in order to fix the semiconductor chip on the circuit board, after mounting the semiconductor chip on the circuit board on which solder bumps are formed. Thereby, there also have been problems of an increase of the number of steps and an decrease of a yield.
Then, as a method for establishing an electric connection between opposed electrode terminals of the semiconductor chip and the circuit board and fixing the semiconductor chip onto the circuit board both at the same time, a flip chip mounting technique using an anisotropic electrically conductive material has been developed. In this technique, by supplying a thermosetting resin containing electrically conductive particles between the circuit board and the semiconductor chip, and then heating the thermosetting resin while applying pressure to the semiconductor chip at the same time, it is possible to establish the electric connection between the electrode terminals of the semiconductor chip and the circuit board and fix the semiconductor chip to the circuit board at the same time (for example, see Patent document 3).
However, in both of the solder paste method described in Patent document 1 and the super solder method described in Patent document 2, since the paste-like composition simply is supplied onto the circuit board by application, local variations in thickness and concentration occur, resulting in variations in the solder deposition amount for individual electrode terminals. Consequently, it is not possible to achieve solder bumps with uniform heights. Also, in these methods, since the paste-like composition is supplied by application onto the circuit board whose surface is provided with the electrode terminals, namely, with projections or depressions, a sufficient amount of solder cannot be supplied onto the electrode terminals serving as the projections, making it difficult to achieve a desired solder bump height necessary for the flip chip mounting.
Moreover, in the flip chip mounting method described in Patent document 3, there are many problems in productivity and reliability that are to be solved as described below.
Firstly, since the electric conduction between the electrode terminals is obtained by mechanical contact via the electrically conductive particles, it is difficult to achieve a stable conductive state. Secondarily, since a distance varies depending on an amount of the electrically conductive particles that are present between the electrode terminals of the semiconductor chip and the circuit board, the electric connection is unstable. Thirdly, in the heating process for curing the thermosetting resin, the electrically conductive particles are scattered, which causes a decrease of a yield due to a short circuit generated thereby. Fourthly, because of a structure where a connection part between the semiconductor chip and the circuit board is exposed and sinks into moisture or the like, and a life span and reliability of the circuit board deteriorate.
Patent document 1: JP 2000-94179 A
Patent document 2: JP1 (1989)-157796 A
Patent document 3: JP2000-332055 A